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AD6684 Datasheet(PDF) 82 Page - Analog Devices

Part # AD6684
Description  135 MHz Quad IF Receiver
PDF  107 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD6684 Datasheet(HTML) 82 Page - Analog Devices

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AD6684
Data Sheet
Rev. 0 | Page 82 of 107
MEMORY MAP DETAILS
All address locations that are not included in Table 46 are not currently supported for this device and must not be written.
Table 46. Memory Map Details
Address
Name
Bits
Bit Name
Settings
Description
Reset
Access
0x0000
Global Map
SPI Config-
uration A
7
Soft reset (self clearing)
When a soft reset is issued, the user must
wait 5 ms before writing to any other
register. This wait provides sufficient time
for the boot loader to complete.
0x0
R/W
0
Do nothing.
1
Reset the SPI and registers (self clearing).
6
LSB first mirror
0x0
R/W
1
LSB shifted first for all SPI operations.
0
MSB shifted first for all SPI operations.
5
Address ascension mirror
0x0
R/W
0
Multibyte SPI operations cause addresses
to auto-increment.
1
Multibyte SPI operations cause addresses
to auto-increment.
[4:3]
Reserved
Reserved.
0x0
R
2
Address ascension
0x0
R/W
0
Multibyte SPI operations cause addresses
to autoincrement.
1
Multibyte SPI operations cause addresses
to auto increment.
1
LSB first
0x0
R/W
1
LSB shifted first for all SPI operations.
0
MSB shifted first for all SPI operations.
0
Soft reset (self clearing)
When a soft reset is issued, the user must
wait 5 ms before writing to any other
register. This wait provides sufficient time
for the boot loader to complete.
0x0
R/W
0
Do nothing.
1
Reset the SPI and registers (self clearing).
0x0001
Global Map
SPI Config-
uration B
7
Single instruction
0x0
R/W
0
SPI streaming enabled.
1
Streaming (multibyte read/write) is
disabled. Only one read or write operation
is performed, regardless of the state of the
CSB line.
[6:2]
Reserved
Reserved.
0x0
R
1
Datapath soft reset (self
clearing)
0x0
R/W
0
Normal operation.
1
Datapath soft reset (self-clearing).
0
Reserved
Reserved.
0x0
R
0x0002
Channel map
chip config-
uration
[7:2]
Reserved
Reserved.
0x0
R
[1:0]
Channel power modes
Channel power modes.
0x0
R/W
00
Normal mode (power up).
10
Standby mode. The digital datapath clocks
are disabled, the JESD204B interface is
enabled, and the outputs are enabled.
11
Power-down mode. The digital datapath
clocks are disabled, the digital datapath is
held in reset, the JESD204B interface is
disabled, and the outputs are disabled.



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