AD6684 datasheet(63/107 Pages) AD

63 / 107 page

Data Sheet

AD6684

Rev. 0 | Page 63 of 107

Example 2: ADC with NSR Option (Two ADCs + NSR in

Each Pair)

The chip application mode is NSR mode (see Figure 100) with

the following characteristics:



Two 14-bit converters at 500 MSPS



NSR blocks enabled for each channel



Chip decimation ratio = 1

The JESD204B output configuration is as follows:



Virtual converters required = 2 (see Table 33).



Output sample rate (fOUT) = 500 MSPS



N΄ = 16 bits



N = 9 bits



L = 2, M = 2, and F = 2 (quick configuration = 0x49)



CS = 0 to 2



K = 32



Output serial lane rate = 10 Gbps per lane (L = 2)



Set Bits[7:4] to 0x0 in Register 0x056E

JESD204B

TRANSMIT

INTERFACE

(JTX)

1 OR 2 LANES

REAL

CONVERTER 0

AT 500MSPS

AT UP TO 15Gbps

NSR

(21% OR 28%

BANDWIDTH)

14-BIT ADC

CORE

AT 500MSPS

14-BIT ADC

CORE

AT 500MSPS

14-BIT ADC

CORE

AT 500MSPS

14-BIT ADC

CORE

AT 500MSPS

REAL

CONVERTER 1

AT 500MSPS

NSR

(21% OR 28%

BANDWIDTH)

CONVERTER 0

AT 500MSPS

NSR

(21% OR 28%

BANDWIDTH)

CONVERTER 1

AT 500MSPS

NSR

(21% OR 28%

BANDWIDTH)

JESD204B

TRANSMIT

INTERFACE

(JTX)

1 OR 2 LANES

AT UP TO 15Gbps

Figure 100. Two ADC + NSR Mode

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