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AD6684 Datasheet(PDF) 59 Page - Analog Devices |
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AD6684 Datasheet(HTML) 59 Page - Analog Devices |
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59 / 107 page ![]() Data Sheet AD6684 Rev. 0 | Page 59 of 107 JESD204B Tx CONVERTER MAPPING To support the different chip operating modes, the AD6684 design treats each sample stream (real or I/Q) as originating from separate virtual converters. The I/Q samples are always mapped in pairs with the I samples mapped to the first virtual converter and the Q samples mapped to the second virtual converter. With this transport layer mapping, the number of virtual converters are the same whether A single real converter is used along with a digital downconverter block producing I/Q outputs, or An analog downconversion is used with two real converters producing I/Q outputs. Figure 97 shows a block diagram of the two scenarios described for I/Q transport layer mapping. The JESD204B Tx block for AD6684 supports up to four DDC blocks. Each DDC block outputs either two sample streams (I/Q) for the complex data components (real + imaginary), or one sample stream for real (I) data. The JESD204B interface can be configured to use up to eight virtual converters depending on the DDC configuration. Figure 98 shows the virtual converters and their relationship to the DDC outputs when complex outputs are used. Table 33 shows the virtual converter mapping for each chip operating mode when channel swapping is disabled. REAL I Q I CONVERTER 0 Q CONVERTER 1 ADC ADC 90° PHASE Σ JESD204B Tx L LANES I/Q ANALOG MIXING M = 2 ADC REAL REAL I CONVERTER 0 Q CONVERTER 1 JESD204B Tx L LANES DIGITAL DOWNCONVERSION M = 2 DIGITAL DOWNCONVERSION Figure 97. I/Q Transport Layer Mapping DDC 0 I Q I Q REAL/I CONVERTER 0 Q CONVERTER 1 REAL/I REAL/Q DDC 1 I Q I Q REAL/I CONVERTER 2 Q CONVERTER 3 REAL/I REAL/Q DDC 0 I Q I Q REAL/I CONVERTER 4 Q CONVERTER 5 REAL/I REAL/Q DDC 1 I Q I Q REAL/I CONVERTER 6 Q CONVERTER 7 REAL/I REAL/Q I/Q CROSSBAR MUX I/Q CROSSBAR MUX OUTPUT INTERFACE OUTPUT INTERFACE ADC SAMPLING AT fS REAL/I ADC SAMPLING AT fS REAL/Q ADC A SAMPLING AT fS REAL/I ADC SAMPLING AT fS REAL/Q Figure 98. DDCs and Virtual Converter Mapping |
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