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AD6684 Datasheet(PDF) 99 Page - Analog Devices

Part # AD6684
Description  135 MHz Quad IF Receiver
PDF  107 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD6684 Datasheet(HTML) 99 Page - Analog Devices

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Data Sheet
AD6684
Rev. 0 | Page 99 of 107
Address
Name
Bits
Bit Name
Settings
Description
Reset
Access
1
FACI
0x0
R/W
0
Frame alignment character insertion
enabled (JESD204B, Section 5.3.3.4).
1
Frame alignment character insertion
disabled; for debug only (JESD204B,
Section 5.3.3.4)
0
Link control
0x0
R/W
0
JESD204B serial transmit link enabled.
Transmission of the /K28.5/ characters for
code group synchronization is controlled
by the SYNCINB±x signal pin.
1
JESD204B serial transmit link powered
down (held in reset and clock gated).
0x0572
JESD204B
map JTX
Link
Control 2
[7:6]
SYNCINB±AB/
SYNCINB±CD pin control
0x0
R/W
00
Normal mode.
10
Ignore SYNCINB±AB/SYNCINB±CD (force
CGS).
11
Ignore SYNCINB±AB/SYNCINB±CD (force
ILAS/user data).
5
SYNCINB±AB/
SYNCINB±CD pin invert
0x0
R/W
0
SYNCINB±AB/SYNCINB±CD pin not inverted.
1
SYNCINB±AB/SYNCINB±CD pin inverted.
4
SYNCINB±AB/
SYNCINB±CD pin type
0x0
R/W
0
LVDS differential pair SYNC signal input.
1
CMOS single-ended SYNC signal input.
3
Reserved
Reserved.
0x0
R
2
8-bit/10-bit bypass
0x0
R/W
0
8-bit/10-bit enabled.
1
8-bit/10-bit bypassed (the most significant
two bits are 0).
1
8-bit/10-bit bit invert
0x0
R/W
0
Normal.
1
Invert a b c d e f g h i j symbols.
0
Reserved
Reserved.
0x0
R/W
0x0573
JESD204B
map JTX
Link
Control 3
[7:6]
Checksum mode
0x0
R/W
00
Checksum is the sum of all the 8-bit
registers in the link configuration table.
01
Checksum is the sum of all individual link
configuration fields (LSB aligned).
10
Checksum is disabled (set to 0). For test
purposes only.
11
Unused.
[5:4]
Test injection point
0x0
R/W
0
N' sample input.
1
10-bit data at 8-bit/10-bit output (for PHY
testing).
10
8-bit data at scrambler input.



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