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AD6684 Datasheet(PDF) 103 Page - Analog Devices

Part # AD6684
Description  135 MHz Quad IF Receiver
PDF  107 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD6684 Datasheet(HTML) 103 Page - Analog Devices

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Data Sheet
AD6684
Rev. 0 | Page 103 of 107
Address
Name
Bits
Bit Name
Settings
Description
Reset
Access
0x05B2
JESD204B
map JTX
Lane Assign-
ment 1
7
Reserved
Reserved.
0x0
R
[6:4]
Reserved
Reserved.
0x0
R/W
3
Reserved
Reserved.
0x0
R
[2:0]
SERDOUTAB0±/
SERDOUTCD0± lane
assignment
0x0
R/W
0
Logical Lane 0 (default).
1
Logical Lane 1.
0x05B3
JESD204B
map JTX
Lane Assign-
ment 2
7
Reserved
Reserved.
0x0
R
[6:4]
Reserved
Reserved.
0x1
R/W
3
Reserved
Reserved.
0x0
R
[2:0]
SERDOUTAB1±/
SERDOUTCD1± lane
assignment
0x1
R/W
0
Logical Lane 0.
1
Logical Lane 1 (default).
0x05C0
JESD204B
map
JESD204B
serializer
drive adjust
7
Reserved
Reserved.
0x0
R
[6:4]
Swing voltage for
SERDOUTAB1±/
SERDOUTCD1±
0x1
R/W
0
1.0 × DRVDD1 (differential).
1
0.850 × DRVDD1 (differential).
3
Reserved
Reserved.
0x0
R
[2:0]
Swing voltage for
SERDOUTAB0±/
SERDOUTCD0±
0x1
R/W
0
1.0 × DRVDD1 (differential).
0x05C4
JESD204B
serializer
preemphasis
selection
register for
Logical
Lane 0
7
Post tab polarity
Post tab polarity.
0x0
R/W
0
Normal.
1
Inverted.
[6:4]
Sets post tab level
These bits set the post tab level.
0x0
R/W
0
0 dB.
1
3 dB.
10
6 dB.
11
9 dB.
100
12 dB.
101
Not valid.
110
Not valid.
111
Not valid.
3
Pretab polarity
Pretab polarity.
0x0
R/W
0
Normal.
1
Inverted.
[2:0]
Sets pretab level
These bits set the pretab level.
0x0
R/W
0
0 dB.
1
3 dB.
10
6 dB.
11
9 dB.
100
12 dB.
101
Not valid.
110
Not valid.
111
Not valid.



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