AD6684 datasheet(106/107 Pages) AD

106 / 107 page

AD6684

Data Sheet

Rev. 0 | Page 106 of 107

APPLICATIONS INFORMATION

POWER SUPPLY RECOMMENDATIONS

The AD6684 must be powered by the following seven supplies:

AVDD1 = AVDD1_SR = 0.975 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V,

DVDD = 0.975 V, DRVDD1 = 0.975 V, and SPIVDD = 1.8 V. For

applications requiring an optimal high power efficiency and low

noise performance, it is recommended that the ADP5054 quad

switching regulator be used to convert the 6.0 V or 12 V input rails

to intermediate rails (1.3 V, 2.4 V, and 3.0 V). These intermediate

rails are then postregulated by very low noise, low dropout (LDO)

regulators (ADP1762, ADP7159, ADP151, and ADP7118).

Figure 104 shows the recommended power supply scheme for

the AD6684.

AVDD1: 0.95V

1.3V

AVDD1_SR: 0.95V

ADP1762

(LDO)

ADP1762

(LDO)

ADP7159

(LDO)

ADP7159

(LDO)

DVDD: 0.95V

DRVDD1: 0.95V

AVDD2: 1.8V

AVDD3: 2.5V

DRVDD2: 1.8V

6V/12V

INPUT

SPIVDD: 1.8V

2.4V

ADP151

(LDO)

1.3V

FILTER

ADP7118

(LDO)

FILTER

3.0V

ADP5054

(SWITCHING

REGULATOR)

Figure 104. High Efficiency, Low Noise Power Solution for the AD6684

It is not necessary to split all of these power domains in all cases.

The recommended solution shown in Figure 104 provides the

lowest noise, highest efficiency power delivery system for the

AD6684. If only one 0.975 V supply is available, route to AVDD1

first and then tap it off and isolate it with a ferrite bead or a

filter choke, preceded by decoupling capacitors for AVDD1_SR,

DVDD, and DRVDD, in that order. The user can employ several

different decoupling capacitors to cover both high and low

frequencies. These capacitors must be located close to the point

of entry at the PCB level and close to the devices, with minimal

trace lengths.

EXPOSED PAD THERMAL HEAT SLUG

RECOMMENDATIONS

It is required that the exposed pad on the underside of the ADC

be connected to AGND to achieve the best electrical and

thermal performance of the AD6684. Connect an exposed

continuous copper plane on the PCB to the AD6684 exposed

pad, Pin 0. The copper plane must have several vias to achieve

the lowest possible resistive thermal path for heat dissipation to

flow through the bottom of the PCB. These vias must be solder

filled or plugged. The number of vias and the fill determine the

resultant θJA measured on the board (see Table 7).

See Figure 105 for a PCB layout example. For detailed

information on packaging and the PCB layout of chip scale

packages, see the AN-772 Application Note, A Design and

Manufacturing Guide for the Lead Frame Chip Scale Package

(LFCSP).

Figure 105. Recommended PCB Layout of Exposed Pad for the AD6684

AVDD1_SR (PIN 64) AND AGND_SR (PIN 63 AND

PIN 67)

AVDD1_SR (Pin 64) and AGND_SR (Pin 63 and Pin 67) can be

used to provide a separate power supply node to the SYSREF±

circuits of the AD6684. If running in Subclass 1, the AD6684

can support periodic one-shot or gapped signals. To minimize

the coupling of this supply into the AVDD1 supply node,

adequate supply bypassing is needed.

AD6684 Datasheet(PDF) 106 Page - Analog Devices

AD6684 Datasheet(HTML) 106 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL