AD6684 datasheet(57/107 Pages) AD

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Data Sheet

AD6684

Rev. 0 | Page 57 of 107

User Data and Error Detection

After the initial lane alignment sequence is complete, the user

data is sent. Normally, within a frame, all characters are considered

user data. However, to monitor the frame clock and multiframe

clock synchronization, there is a mechanism for replacing

characters with /F/ or /A/ alignment characters when the data

meets certain conditions. These conditions are different for

unscrambled and scrambled data. The scrambling operation is

enabled by default, but it can be disabled using the SPI.

For scrambled data, any 0xFC character at the end of a frame is

replaced with an /F/, and any 0xFD character at the end of a multi-

frame is replaced with an /A/. The JESD204B receiver (Rx)

checks for /F/ and /A/ characters in the received data stream

and verifies that they only occur in the expected locations. If an

unexpected /F/ or /A/ character is found, the receiver handles

the situation by using dynamic realignment or asserting the

SYNCINB± signal for more than four frames to initiate a

resynchronization. For unscrambled data, if the final character

of two subsequent frames are equal, the second character is

replaced with an /F/ if it is at the end of a frame, and an /A/ if it

is at the end of a multiframe.

Insertion of alignment characters can be modified using the

SPI. The frame alignment character insertion (FACI) is enabled

by default. More information on the link controls is available in

the Memory Map section, Register 0x0571.

8-Bit/10-Bit Encoder

The 8-bit/10-bit encoder converts 8-bit octets into 10-bit symbols

and inserts control characters into the stream when needed. The

control characters used in JESD204B are shown in Table 32. The

8-bit/10-bit encoding ensures that the signal is dc balanced by

using the same number of ones and zeros across multiple

symbols.

The 8-bit/10-bit interface has options that can be controlled via

the SPI. These operations include bypass and invert. These options

are intended to be troubleshooting tools for the verification of

the digital front end (DFE). Refer to the Memory Map section,

10-bit encoder.

PHYSICAL LAYER (DRIVER) OUTPUTS

Digital Outputs, Timing, and Controls

The AD6684 physical layer consists of drivers that are defined

in the JEDEC Standard JESD204B, July 2011. The differential

digital outputs are powered up by default. The drivers use a

dynamic 100 Ω internal termination to reduce unwanted

reflections.

Place a 100 Ω differential termination resistor at each receiver

input to result in a nominal 300 mV p-p swing at the receiver

(see Figure 92). Alternatively, single-ended 50 Ω termination

can be used. When single-ended termination is used, the

termination voltage is DRVDD1/2. Otherwise, 0.1 μF

ac coupling capacitors can be used to terminate to any single-

ended voltage.

SERDOUTx+

DRVDD

VRXCM

SERDOUTx–

OUTPUT SWING = 300mV p-p

0.1µF

100Ω

50Ω

0.1µF

RECEIVER

VCM = VRXCM

100Ω

DIFFERENTIAL

TRACE PAIR

Figure 92. AC-Coupled Digital Output Termination Example

Table 32. AD6684 Control Characters used in JESD204B

Abbreviation

Control Symbol

8-Bit Value

10-Bit Value,

RD1 = −1

10-Bit Value,

RD1 = +1

Description

/R/

/K28.0/

000 11100

001111 0100

110000 1011

Start of multiframe

/A/

/K28.3/

011 11100

001111 0011

110000 1100

Lane alignment

/Q/

/K28.4/

100 11100

001111 0100

110000 1101

Start of link configuration data

/K/

/K28.5/

101 11100

001111 1010

110000 0101

Group synchronization

/F/

/K28.7/

111 11100

001111 1000

110000 0111

Frame alignment

1 RD means running disparity.

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