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AD6684 Datasheet(PDF) 87 Page - Analog Devices |
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AD6684 Datasheet(HTML) 87 Page - Analog Devices |
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87 / 107 page  Data Sheet AD6684 Rev. 0 | Page 87 of 107 Address Name Bits Bit Name Settings Description Reset Access 0x0121 Pair map SYSREF Control 2 [7:4] Reserved Reserved. 0x0 R [3:0] SYSREF N shot ignore counter select 0000 Next SYSREF± only (do not ignore). 0x0 R/W 0001 Ignore the first SYSREF± transition. 0010 Ignore the first two SYSREF± transitions. 0011 Ignore the first three SYSREF± transitions. 0100 Ignore the first four SYSREF± transitions. 0101 ignore the first five SYSREF± transitions. 0110 ignore the first six SYSREF± transitions. 0111 ignore the first seven SYSREF± transitions. 1000 ignore the first eight SYSREF± transitions. 1001 ignore the first nine SYSREF± transitions. 1010 ignore the first 10 SYSREF± transitions. 1011 ignore the first 11 SYSREF± transitions. 1100 ignore the first 12 SYSREF± transitions. 1101 ignore the first 13 SYSREF± transitions. 1110 ignore the first 14 SYSREF± transitions. 1111 ignore the first 15 SYSREF± transitions. 0x0123 Pair map SYSREF Control 4 7 Reserved Reserved. 0x0 R [6:0] SYSREF± time stamp delay[6:0] SYSREF± timestamp delay (in converter sample clock cycles) 0x40 R/W 0 0 sample clock cycle delay 1 1 sample clock cycle delay … 127 127 sample clock cycle delay 0x0128 Pair map SYSREF Status 1 [7:4] SYSREF± hold status[7:4] SYSREF± hold status. See Table 37 for more information. 0x0 R [3:0] SYSREF± setup status[3:0] SYSREF± setup status. See Table 37 for more information. 0x0 R 0x0129 Pair map SYSREF Status 2 [7:4] Reserved Reserved. 0x0 R [3:0] Clock divider phase when SYSREF± is captured SYSREF± divider phase. These bits represent the phase of the divider when SYSREF± is captured. 0x0 R 0000 In phase. 0001 SYSREF± is ½ cycle delayed from clock. 0010 SYSREF± is 1 cycle delayed from clock. 0011 1½ input clock cycles delayed. 0100 2 input clock cycles delayed. 0101 2½ input clock cycles delayed. … 1111 7½ input clock cycles delayed. 0x012A Pair map SYSREF Status 3 [7:0] SYSREF± counter [7:0] (increments when a SYSREF± is captured) SYSREF± count. These bits are a running counter that increments whenever a SYSREF± event is captured. Thes bits are reset by Register 0x0120, Bit 6, and wrap around at 255. Read these bits only while Register 0x120, Bits[2:1] are disabled. 0x0 R |
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