AD6684 datasheet(58/107 Pages) AD

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AD6684

Data Sheet

Rev. 0 | Page 58 of 107

The AD6684 digital outputs can interface with custom application

specific integrated circuits (ASICs) and field programmable gate

array (FPGA) receivers, providing superior switching performance

in noisy environments. Single point to point network topologies

are recommended with a single differential 100 Ω termination

resistor placed as close to the receiver inputs as possible. The

common mode of the digital output automatically biases itself

to half the DRVDD1 supply of 1.25 V (VCM = 0.6 V). See Figure 93

for an example of dc coupling the outputs to the receiver logic.

SERDOUTx+

DRVDD

SERDOUTx–

OUTPUT SWING = 300mV p-p

100Ω

RECEIVER

VCM = DRVDD/2

100Ω

DIFFERENTIAL

TRACE PAIR

Figure 93. DC-Coupled Digital Output Termination Example

If there is no far end receiver termination, or if there is poor

differential trace routing, timing errors may result. To avoid

such timing errors, it is recommended that the trace length be

less than six inches, and that the differential output traces be

close together and at equal lengths.

Figure 94, Figure 95, and Figure 96 show examples of the digital

output data eye, time interval error (TIE) jitter histogram, and

bathtub curve, respectively, for one AD6684 lane running at

15 Gbps. The format of the output data is twos complement by

default. To change the output data format, see the Memory Map

section (Register 0x0561 in Table 45 and Table 46).

De-Emphasis

De-emphasis enables the receiver eye diagram mask to be met

in conditions where the interconnect insertion loss does not

meet the JESD204B specification. Use the preemphasis feature

only when the receiver is unable to recover the clock due to

excessive insertion loss. Under normal conditions, preemphasis

is disabled to conserve power. Additionally, enabling and setting

too high a preemphasis value on a short link can cause the

receiver eye diagram to fail. Use the preemphasis setting with

caution because it can increase electromagnetic interference

(EMI). See the Memory Map section (Registers 0x05C4 and

Phase-Locked Loop

The phase-locked loop (PLL) is used to generate the serializer

clock, which operates at the JESD204B lane rate. The status

of the PLL lock can be checked in the PLL lock status bit

(Register 0x056F, Bit 7). This read only bit lets the user know if

the PLL has achieved a lock for the specific setup. The JESD204B

lane rate control bit, Bit 4 of Register 0x056E, must be set to

correspond with the lane rate.

500

–500

–300

–200

–100

100

200

300

–60

–40

–20

TIME (ps)

400

–400

Tx EYE

MASK

Figure 94. AD6684 Digital Outputs Data Eye Diagram; External 100 Ω

Terminations at 15 Gbps

16000

14000

12000

10000

8000

6000

4000

2000

–4

–2

TIME (ps)

Figure 95. AD6684 Digital Outputs Histogram; External 100 Ω Terminations

at 15 Gbps

1–2

1–4

1–6

1–8

1–10

1–12

1–16

1–14

–0.5 –0.4 –0.3

–0.2 –0.1

0.1

0.2

0.3

0.4

0.5

Figure 96. AD6684 Digital Outputs Bathtub Curve; External 100 Ω

Terminations at 15 Gbps

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