AD6684 datasheet(84/107 Pages) AD

84 / 107 page

AD6684

Data Sheet

Rev. 0 | Page 84 of 107

Address

Name

Bits

Bit Name

Settings

Description

Reset

Access

0x0040

Pair Map

Chip Pin

Control 1

[7:6]

PDWN/STBY function

0x0

R/W

Power-down pin—assertion of the external

power-down pin (PDWN/STBY) causes the

chip to enter full power-down mode.

Standby pin—assertion of the external

power-down pin (PDWN/STBY) causes the

chip to enter standby mode.

Pin disabled—assertion of the external

power-down pin (PDWN/STBY) is ignored.

[5:3]

Fast Detect B/Fast Detect D

(FD_B/FD_D)

0x7

R/W

000

Fast Detect B/Fast Detect D output.

001

JESD204B LMFC output.

010

JESD204B internal SYNC signal in the ADC

output.

111

Disabled (configured as an input with a

weak pull down).

[2:0]

Fast Detect A/Fast Detect C

(FD_A/FD_C)

0x7

R/W

000

Fast Detect A/Fast Detect C output.

001

JESD204B LMFC output.

010

JESD204B internal SYNC signal in the ADC

output.

111

Disabled (configured as an input with a

weak pull down).

0x0108

Pair map

clock divider

control

[7:3]

Reserved

Reserved.

0x0

[2:0]

Clock divider

0x1

R/W

000

Divide by 1.

001

Divide by 2.

011

Divide by 4.

111

Divide by 8.

0x0109

Channel

map clock

divider

phase

[7:4]

Reserved

Reserved.

0x0

[3:0]

Clock divider phase offset

0x0

R/W

0000

0 input clock cycles delayed.

0001

1/2 input clock cycles delayed (invert clock).

0010

1 input clock cycles delayed.

0011

1 1/2 input clock cycles delayed.

0100

2 input clock cycles delayed.

0101

2 1/2 input clock cycles delayed.

0110

3 input clock cycles delayed.

0111

3 1/2 input clock cycles delayed.

1000

4 input clock cycles delayed.

1001

4 1/2 input clock cycles delayed.

1010

5 input clock cycles delayed.

1011

5 1/2 input clock cycles delayed.

1100

6 input clock cycles delayed.

1101

6 1/2 input clock cycles delayed.

1110

7 input clock cycles delayed.

1111

7 1/2 input clock cycles delayed.

AD6684 Datasheet(PDF) 84 Page - Analog Devices

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