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AD6684 Datasheet(PDF) 85 Page - Analog Devices |
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AD6684 Datasheet(HTML) 85 Page - Analog Devices |
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85 / 107 page  Data Sheet AD6684 Rev. 0 | Page 85 of 107 Address Name Bits Bit Name Settings Description Reset Access 0x010A Pair map clock divider SYSREF control 7 Clock divider auto phase adjust 0x0 R/W 0 Clock divider phase is not changed by SYSREF (disabled). 1 Clock divider phase is automatically adjusted by SYSREF (enabled). [6:4] Reserved Reserved. 0x0 R [3:2] Clock divider negative skew window 0x0 R/W 00 No negative skew; SYSREF must be captured accurately. 01 1/2 device clock of negative skew. 10 1 device clocks of negative skew. 11 1 1/2 device clocks of negative skew. [1:0] Clock divider positive skew window 0x0 R/W 00 No positive skew; SYSREF must be captured accurately. 01 1/2 device clock of positive skew. 10 1 device clocks of positive skew. 11 1 1/2 device clocks of positive skew. 0x0110 Pair map clock delay control [7:3] Reserved Reserved. 0x0 R [2:0] Clock delay mode select Clock delay mode select; used in conjunction with Register 0x0111 and Register 0x0112. 0x0 R/W 000 No clock delay. 001 Reserved. 010 Fine delay; only Delay Step 0 to Delay Step 16 are valid. 011 Fine delay (lowest jitter); only Delay Step 0 to Delay Step 16 are valid. 100 Fine delay; all 192 delay steps are valid. 101 Reserved (same as 001). 110 Fine delay enabled; all 192 delay steps are valid. Super fine delay enabled (all 128 delay steps are valid). 0x0111 Channel map clock super fine delay [7:0] Clock super fine delay adjust This is an unsigned control to adjust the super fine sample clock delay in 0.25 ps steps. 0x0 R/W 0x00 0 delay steps. … 0x08 8 delay steps. … 0x80 128 delay steps. These bits are only used when Register 0x0110, Bits[2:0] = 0x2 or 0x6. 0x0112 Channel map clock fine delay [7:0] Clock fine delay adjust Clock fine delay adjust. This is an unsigned control to adjust the fine sample clock skew in 1.725 ps steps. 0xC0 R/W 0x00 0 delay steps. … 0x08 8 delay steps. … 0xC0 192 delay steps. These bits are only used when Register 0x0110, Bits[2:0] = 0x2, 0x3, 0x4, or 0x6. |
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