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AD6684 Datasheet(PDF) 55 Page - Analog Devices

Part # AD6684
Description  135 MHz Quad IF Receiver
PDF  107 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD6684 Datasheet(HTML) 55 Page - Analog Devices

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Data Sheet
AD6684
Rev. 0 | Page 55 of 107
MUX/
FORMAT
(SPI REGISTERS:
0x0561, 0x0564)
MUX/
FORMAT
(SPI REGISTERS:
0x0561, 0x0564)
JESD204B PAIR
A/B LINK
CONTROL
(L, M, F)
(SPI REGISTER
0x0570)
JESD204B PAIR
A/B LINK
CONTROL
(L, M, F)
(SPI REGISTER
0x0570)
LANE MUX
AND MAPPING
(SPI
REGISTERS:
0x05B0,
0x05B2,
0x05B3)
LANE MUX
AND MAPPING
(SPI
REGISTERS:
0x05B0,
0x05B2,
0x05B3)
CONVERTER A
INPUT
CONVERTER B
INPUT
CONVERTER C
INPUT
CONVERTER D
INPUT
ADC A
ADC B
ADC C
ADC D
SERDOUTAB0+
SERDOUTAB0–
SERDOUTAB1+
SERDOUTAB1–
SERDOUTCD0+
SERDOUTCD0–
SERDOUTCD1+
SERDOUTCD1–
SYSREF±
SYNCINAB±
SYNCINCD±
Figure 88. Transmit Link Simplified Block Diagram Showing Full Bandwidth Mode (Register 0x0200 = 0x00)
JESD204B SAMPLE
CONSTRUCTION
SERDOUTAB0±/
SERDOUTCD0±/
SERDOUTAB0±/
SERDOUTCD0±/
TAIL BITS
REG 0x0571[6]
FRAME
CONSTRUCTION
SCRAMBLER
1 +
x14 + x15
(OPTIONAL)
8-BIT/10-BIT
ENCODER
SERIALIZER
ADC
ADC TEST PATTERNS
(REG 0x0550,
REG 0x0551 TO REG 0x0558)
JESD204B LONG
TRANSPORT TEST
PATTERN
REG 0x0571[5]
JESD204B DATA
LINK LAYER TEST
PATTERNS
REG 0x0574[2:0]
MSB
LSB
SYMBOL0
SYMBOL1
a
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
C2
T
MSB
LSB
S7
S6
S5
S4
S3
S2
S1
S0
MSB
LSB
b c d e f g h i j
a b . . . .
. . . .
a b
i j
i j
a b c d e f g h i j
C2
C1
C0
CONTROL BITS
JESD204B
INTERFACE TEST
PATTERNS
(REG 0x0573,
REG 0x0551 TO REG 0x0558)
S7
S6
S5
S4
S3
S2
S1
S0
Figure 89. ADC Output Data
path Showing Data Framing
TRANSPORT
LAYER
PHYSICAL
LAYER
DATA LINK
LAYER
Tx
OUTPUT
SAMPLE
CONSTRUCTION
FRAME
CONSTRUCTION
SCRAMBLER
ALIGNMENT
CHARACTER
GENERATION
8-BIT/10-BIT
ENCODER
CROSSBAR
MUX
SERIALIZER
PROCESSED
SAMPLES
FROM ADC
SYSREF±
SYNCINB±
Figure 90. Data Flow



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