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AD6684 Datasheet(PDF) 96 Page - Analog Devices |
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AD6684 Datasheet(HTML) 96 Page - Analog Devices |
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96 / 107 page ![]() AD6684 Data Sheet Rev. 0 | Page 96 of 107 Address Name Bits Bit Name Settings Description Reset Access 0x0430 Pair map VDR control 7 Reserved Reserved. 0x0 R/W [6:5] Reserved Reserved. 0x0 R 4 Reserved Reserved. 0x0 R/W [3:2] Reserved Reserved. 0x0 R 1 VDR bandwidth 0x0 R/W 0 25% BW mode. 1 43% BW mode. Only available in complex mode. 0 VDR complex mode enable 0x1 R/W 0 Dual real mode. Ignore Bit 1. 1 Dual complex mode. Complex input, Channel A/Channel C are I and Channel B/Channel D are Q. 0x0434 Channel map VDR tuning frequency [7:4] Reserved Reserved. 0x0 R [3:0] VDR center frequency See the Variable Dynamic Range (VDR) section for details. 0x0 R/W 0x0550 Channel map test mode control 7 User pattern selection 0x0 R/W 0 Continuous repeat. 1 Single pattern. 6 Reserved Reserved. 0x0 R 5 Reset PN long generation 0x0 R/W 0 Long PN enabled. 1 Long PN held in reset. 4 Reset PN short generation 0x0 R/W 0 Short PN enabled. 1 Short PN held in reset. [3:0] Test mode selection 0x0 R/W 0000 Off—normal operation. 0001 Midscale short. 0010 Positive full scale. 0011 Negative full scale. 0100 Alternating checker board. 0101 PN sequence—long. 0110 PN sequence—short. 0111 1/0 word toggle. 1000 User pattern test mode (used with the test mode patern selection and the User Pattern 1 through User Pattern 4 registers) 1111 Ramp output. 0x0551 Pair map User Pattern 1 LSB [7:0] User Pattern 1[7:0] User Test Pattern 1 least significant byte 0x0 R/W 0x0552 Pair map User Pattern 1 MSB [7:0] User Pattern 1[15:8] User Test Pattern 1 most significant byte 0x0 R/W 0x0553 Pair map User Pattern 2 LSB [7:0] User Pattern 2[7:0] User Test Pattern 2 least significant byte 0x0 R/W 0x0554 Pair map User Pattern 2 MSB [7:0] User Pattern 2[15:8] User Test Pattern 2 most significant byte 0x0 R/W 0x0555 Pair map User Pattern 3 LSB [7:0] User Pattern 3[7:0] User Test Pattern 3 least significant byte 0x0 R/W |
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