AD6684 datasheet(60/107 Pages) AD

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AD6684

Data Sheet

Rev. 0 | Page 60 of 107

SETTING UP THE AD6684 DIGITAL INTERFACE

The following SPI writes are required for the AD6684 at startup

and each time the ADC is reset (datapath reset, soft reset, link

power-down/power-up, or hard reset):

Write 0x4F to Register 0x1228.

Write 0x0F to Register 0x1228.

Write 0x04 to Register 0x1222.

Write 0x00 to Register 0x1222.

Write 0x08 to Register 0x1262.

Write 0x00 to Register 0x1262.

The AD6684 has two JESD204B links. The device offers an easy

way to set up the JESD204B link through the JESD04B quick

configuration register (Register 0x0570). The serial outputs

(SERDOUTABx± and SERDOUTCDx±) are considered to be

part of one JESD204B link. The basic parameters that determine

the link setup are



Number of lanes per link (L)



Number of converters per link (M)



Number of octets per frame (F)

If the internal DDCs are used for on-chip digital processing, M

represents the number of virtual converters. The virtual

converter mapping setup is shown in Figure 98.

The maximum lane rate allowed by the JESD204B specification

is 15 Gbps. The lane line rate is related to the JESD204B

parameters using the following equation:

Lane Line Rate =

OUT

















where:

Ratio

Decimation

CLOCK

ADC

OUT



The decimation ratio (DCM) is the parameter programmed in

Use the following steps to configure the output:

Power down the link.

Select quick configuration options.

Configure detailed options

Set output lane mapping (optional).

Set additional driver configuration options (optional).

Power up the link.

If the lane line rate calculated is less than 6.25 Gbps, select the

low line rate option by programming a value of 0x10 to

Table 34 and Table 35 show the JESD204B output configurations

for both N΄ = 16 and N΄ = 8 for a given number of virtual

converters. Take care to ensure that the serial line rate for given

configuration is within the supported range of 1.5625 Gbps to

15 Gbps.

Table 33. Virtual Converter Mapping (Per Link)

Number of Virtual

Converters Supported

Chip Application Mode

(Register 0x0200,

Bits[3:0])

Chip Q Ignore

(Register 0x0200,

Bit 5)

Virtual Converter Mapping

1 to 2

Full bandwidth mode (0x0)

Real or complex (0x0)

ADC A/C

samples

ADC B/D

samples

Unused

One DDC mode (0x1)

Real (I only) (0x1)

DDC 0

I samples

Unused

One DDC mode (0x1)

Complex (I/Q) (0x0)

DDC 0

I samples

DDC 0

Q samples

Unused

Two DDC mode (0x2)

Real (I only) (0x1)

DDC 0

I samples

DDC 1

I samples

Unused

Two DDC mode (0x2)

Complex (I/Q) (0x0)

DDC 0

I samples

DDC 0

Q samples

DDC 1

I samples

DDC 1

Q samples

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