 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AD6684 Datasheet(PDF) 89 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD6684 Datasheet(HTML) 89 Page - Analog Devices |
|
|
89 / 107 page  Data Sheet AD6684 Rev. 0 | Page 89 of 107 Address Name Bits Bit Name Settings Description Reset Access 0x0247 Channel map fast detect upper thres- hold LSB [7:0] Fast detect upper threshold [7:0] LSBs of fast detect upper threshold. Eight LSBS of the programmable 13-bit upper threshold that is compared to the fine ADC magnitude. 0x0 R/W 0x0248 Channel map fast detect upper thres- hold MSB [7:5] Reserved Reserved. 0x0 R [4:0] Fast detect upper threshold[12:8] LSBs of fast detect upper threshold. Eight LSBS of the programmable 13-bit upper threshold that is compared to the fine ADC magnitude. 0x0 R/W 0x0249 Channel map fast detect lower thres- hold LSB [7:0] Fast detect lower threshold[7:0] LSBs of fast detect lower threshold. Eight LSBS of the programmable 13-bit lower threshold that is compared to the fine ADC magnitude 0x0 R/W 0x024A Channel map fast detect lower threshold MSB [7:5] Reserved Reserved. 0x0 R [4:0] Fast detect lower threshold[12:8] LSBs of fast detect lower threshold. Eight LSBS of the programmable 13-bit lower threshold that is compared to the fine ADC magnitude 0x0 R/W 0x024B Channel map fast detect dwell time LSB [7:0] Fast detect dwell time[7:0] LSBs of fast detect dwell time counter target. This target is a load value for a 16-bit counter that determines how long the ADC data must remain below the lower threshold before the FD_x pins are reset to 0 0x0 R/W 0x024C Channel map fast detect dwell time MSB [7:0] Fast detect dwell time[15:8] LSBs of fast detect dwell time counter target. This target is a load value for a 16-bit counter that determines how long the ADC data must remain below the lower threshold before the FDD_x pins are reset to 0. 0x0 R/W 0x026F Pair map signal monitor sync control [7:2] Reserved Reserved. 0x0 R 1 Reserved Reserved. 0x0 R/W 0 Signal monitor synchronization mode 0x0 R/W 0 Synchronization disabled. 1 Only the next valid edge of the SYSREF± pin is used to synchronize the signal monitor block. Subsequent edges of the SYSREF± pin are ignored. After the next SYSREF± is received, this bit is cleared. Note that the SYSREF± input pin must be enabled to synchronize the signal monitor blocks. 0x0270 Channel map signal monitor control [7:2] Reserved Reserved. 0x0 R 1 Peak detector 0x0 R/W 0 Peak detector disabled. 1 Peak detector enabled. 0 Reserved Reserved. 0x0 R 0x0271 Channel map Signal Monitor Period 0 [7:0] Signal monitor period[7:0] This 24-bit value sets the number of output clock cycles over which the signal monitor performs its operation. Bit 0 is ignored. 0x80 R/W 0x0272 Channel map Signal Monitor Period 1 [7:0] Signal monitor period[15:8] This 24-bit value sets the number of output clock cycles over which the signal monitor performs its operation. Bit 0 is ignored. 0x0 R/W 0x0273 Channel map Signal Monitor Period 2 [7:0] Signal monitor period[23:16] This 24-bit value sets the number of output clock cycles over which the signal monitor performs its operation. Bit 0 is ignored. 0x0 R/W |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
