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AD6684 Datasheet(PDF) 91 Page - Analog Devices |
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AD6684 Datasheet(HTML) 91 Page - Analog Devices |
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91 / 107 page ![]() Data Sheet AD6684 Rev. 0 | Page 91 of 107 Address Name Bits Bit Name Settings Description Reset Access 0x0300 Pair map DDC sync control [7:6] Reserved Reserved. 0x0 R/W 5 Reserved Reserved. 0x0 R 4 DDC NCO soft reset This bit can be used to synchronize all the NCOs inside the DDC blocks. 0x0 R/W 0 Normal operation. 1 DDC held in reset. [3:2] Reserved Reserved. 0x0 R 1 DDC next sync The SYSREF± pin must be an integer mul- tiple of the NCO frequency for this function to operate correctly in continuous mode. 0x0 R/W 0 Continuous mode. 1 Only the next valid edge of the SYSREF± pin is used to synchronize the NCO in the DDC block. Subsequent edges of the SYSREF± pin are ignored. Aftwr the next SYSREF is found, the DDC synchronization enable bit is cleared. 0 DDC synchronization mode The SYSREF± input pin must be enabled to synchronize the DDCs. 0x0 R/W 0 Synchronization disabled. 1 If the DDC next syncbit = 1, only the next valid edge of the SYSREF± pin is used to synchronize the NCO in the DDC block. Subsequent edges of the SYSREF± pin are ignored. After the next SYSREF± is received, this bit is cleared. 0x0310 Pair map DDC 0 control 7 DDC 0 mixer select 0x0 R/W 0 Real mixer (I and Q inputs must be from the same real channel). 1 Complex mixer (I and Q must be from separate real and imaginary quadrature ADC receive channels—analog demodulator). 6 DDC 0 gain select Gain can be used to compensate for the 6 dB loss associated with mixing an input signal down to baseband and filtering out its negative component. 0x0 R/W 0 0 dB gain. 1 6 dB gain (multiply by 2). [5:4] DDC 0 IF mode 0x0 R/W 00 Variable IF mode. 01 0 Hz IF mode. 10 fS/4 Hz IF mode. 11 Test mode. 3 DDC 0 complex to real enable 0x0 R/W 0 Complex (I and Q) outputs contain valid data. 1 Real (I) output only. Complex to real enabled. Uses extra fS/4 mixing to convert to real. 2 Reserved Reserved. 0x0 R |
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