Electronic Components Datasheet Search
  English  ▼

X  

AD6684 Datasheet(PDF) 91 Page - Analog Devices

Part # AD6684
Description  135 MHz Quad IF Receiver
PDF  107 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD6684 Datasheet(HTML) 91 Page - Analog Devices

Back Button AD6684 Datasheet HTML 87Page - Analog Devices AD6684 Datasheet HTML 88Page - Analog Devices AD6684 Datasheet HTML 89Page - Analog Devices AD6684 Datasheet HTML 90Page - Analog Devices AD6684 Datasheet HTML 91Page - Analog Devices AD6684 Datasheet HTML 92Page - Analog Devices AD6684 Datasheet HTML 93Page - Analog Devices AD6684 Datasheet HTML 94Page - Analog Devices AD6684 Datasheet HTML 95Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 91 / 107 page
background image
Data Sheet
AD6684
Rev. 0 | Page 91 of 107
Address
Name
Bits
Bit Name
Settings
Description
Reset
Access
0x0300
Pair map
DDC sync
control
[7:6]
Reserved
Reserved.
0x0
R/W
5
Reserved
Reserved.
0x0
R
4
DDC NCO soft reset
This bit can be used to synchronize all the
NCOs inside the DDC blocks.
0x0
R/W
0
Normal operation.
1
DDC held in reset.
[3:2]
Reserved
Reserved.
0x0
R
1
DDC next sync
The SYSREF± pin must be an integer mul-
tiple of the NCO frequency for this function
to operate correctly in continuous mode.
0x0
R/W
0
Continuous mode.
1
Only the next valid edge of the SYSREF± pin
is used to synchronize the NCO in the DDC
block. Subsequent edges of the SYSREF±
pin are ignored. Aftwr the next SYSREF is
found, the DDC synchronization enable bit
is cleared.
0
DDC synchronization
mode
The SYSREF± input pin must be enabled to
synchronize the DDCs.
0x0
R/W
0
Synchronization disabled.
1
If the DDC next syncbit = 1, only the next
valid edge of the SYSREF± pin is used to
synchronize the NCO in the DDC block.
Subsequent edges of the SYSREF± pin are
ignored. After the next SYSREF± is
received, this bit is cleared.
0x0310
Pair map
DDC 0
control
7
DDC 0 mixer select
0x0
R/W
0
Real mixer (I and Q inputs must be from
the same real channel).
1
Complex mixer (I and Q must be from
separate real and imaginary quadrature ADC
receive channels—analog demodulator).
6
DDC 0 gain select
Gain can be used to compensate for the
6 dB loss associated with mixing an input
signal down to baseband and filtering out
its negative component.
0x0
R/W
0
0 dB gain.
1
6 dB gain (multiply by 2).
[5:4]
DDC 0 IF mode
0x0
R/W
00
Variable IF mode.
01
0 Hz IF mode.
10
fS/4 Hz IF mode.
11
Test mode.
3
DDC 0 complex to real
enable
0x0
R/W
0
Complex (I and Q) outputs contain valid
data.
1
Real (I) output only. Complex to real enabled.
Uses extra fS/4 mixing to convert to real.
2
Reserved
Reserved.
0x0
R



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com