AD6684 datasheet(9/107 Pages) AD

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Data Sheet

AD6684

Rev. 0 | Page 9 of 107

SWITCHING SPECIFICATIONS

AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.8 V,

SPIVDD = 1.8 V, specified maximum sampling rate, clock divider = 4, 1.8 V p-p full-scale differential input, 0.5 V internal reference, AIN =

−1.0 dBFS, default SPI settings, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction

temperature (TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 50°C (TA = 25°C).

Table 4.

Parameter

Min

Typ

Max

Unit

CLOCK

Clock Rate at CLK+/CLK− Pins

0.3

2.4

GHz

Maximum Sample Rate1

500

MSPS

Minimum Sample Rate2

240

MSPS

Clock Pulse Width High

125

Clock Pulse Width Low

125

OUTPUT PARAMETERS

Unit Interval (UI)3

62.5

100

Rise Time (tR) (20% to 80% into 100 Ω Load)

31.25

Fall Time (tF) (20% to 80% into 100 Ω Load)

31.37

Phase-Locked Loop (PLL) Lock Time

Data Rate per Channel (NRZ)4

1.5625

Gbps

LATENCY5

Pipeline Latency

Sample clock cycles

Fast Detect Latency

Sample clock cycles

APERTURE

Aperture Delay (tA)

160

Aperture Uncertainty (Jitter, tj)

fs rms

Out-of-Range Recovery Time

Sample clock cycles

1 The maximum sample rate is the clock rate after the divider.

2 The minimum sample rate operates at 240 MSPS with L = 2 or L = 1. Refer to SPI Register 0x011A to reduce the threshold of the clock detect circuit.

3 Baud rate = 1/UI. A subset of this range can be supported.

4 Default L = 2. This number can be changed based on the sample rate and decimation ratio.

5 No DDCs used. L = 2, M = 2, F = 2 for each link.

TIMING SPECIFICATIONS

Table 5.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

CLK+ to SYSREF+ TIMING REQUIREMENTS

See Figure 3

tSU_SR

Device clock to SYSREF+ setup time

−44.8

tH_SR

Device clock to SYSREF+ hold time

64.4

SPI TIMING REQUIREMENTS

See Figure 4

tDS

Setup time between the data and the rising edge of SCLK

tDH

Hold time between the data and the rising edge of SCLK

tCLK

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

tHIGH

Minimum period that SCLK must be in a logic high state

tLOW

Minimum period that SCLK must be in a logic low state

tACCESS

Maximum time delay between falling edge of SCLK and output

data valid for a read operation

tDIS_SDIO

Time required for the SDIO pin to switch from an output to an

input relative to the CSB rising edge (not shown in Figure 4)

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