AD6684 datasheet(88/107 Pages) AD

88 / 107 page

AD6684

Data Sheet

Rev. 0 | Page 88 of 107

Address

Name

Bits

Bit Name

Settings

Description

Reset

Access

0x01FF

Pair map

chip sync

[7:1]

Reserved

Reserved.

0x0

Synchronization mode

0x0

R/W

0x0

Sample synchronization mode. The

SYSREF± signal resets all internal sample

dividers. Use this mode when synchronizing

multiple chips as specified in the JESD204B

standard. If the phase of any of the dividers

must change, the JESD204B link is

interrupted.

0x1

Partial synchronization/timestamp mode.

The SYSREF± signal does not reset sample

internal dividers. In this mode, the JESD204B

link, the signal monitor, and the parallel

interface clocks are not affected by the

SYSREF± signal. The SYSREF signal simply

time stamps a sample as it passes through

the ADC.

0x0200

Pair map

chip mode

[7:6]

Reserved

Reserved.

0x0

R/W

Chip Q ignore

Chip real (I) only selection.

0x0

R/W

Both real (I) and complex (Q) selected.

Only real (I) selected. Complex (Q) is ignored.

Reserved

Reserved.

0x0

[3:0]

Chip application mode

0x7

R/W

0000

Full bandwidth mode.

0001

One DDC mode (DDC 0 only).

0010

Two DDC mode (DDC 0 and DDC 1 only).

0111

Noise shaped requantizer (NSR) mode.

1000

Variable dynamic range (VDR) mode.

0x0201

Pair map

chip dec-

imation ratio

[7:3]

Reserved

Reserved.

0x0

[2:0]

Chip decimation ratio

select

Chip decimation ratio.

0x0

R/W

000

Decimate by 1 (full sample rate).

001

Decimate by 2.

010

Decimate by 4.

011

Decimate by 8.

100

Decimate by 16.

0x0228

Channel map

custom

offset

[7:0]

Offset adjust in LSBs from

+127 to −128

Digital datapath offset. Twos complement

offset adjustment aligned with least

significant converter resolution bit.

0x0

R/W

0x0245

Channel

map fast

detect

control

[7:4]

Reserved

Reserved.

0x0

Force FD_A/FD_B/FD_C/

FD_D pins

0x0

R/W

Normal operation of the fast detect pin.

Force a value on the fast detect pin (see

Bit 2 of this register).

Force value of FD_A/FD_B/

FD_C/FD_D pins; if force

pins is true, this value is

output on the fast detect

pins

The fast detect output pin for this channel

is set to this value when the output is

forced.

0x0

R/W

Reserved

Reserved.

0x0

Enable fast detect output

0x0

R/W

Fine fast detect disabled.

Fine fast detect enabled.

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