AD6684 datasheet(41/107 Pages) AD

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Data Sheet

AD6684

Rev. 0 | Page 41 of 107

FIR FILTERS

GENERAL DESCRIPTION

There are four sets of decimate by 2, low-pass, half-band, FIR

filters (labeled HB1 FIR, HB2 FIR, HB3 FIR, and HB4 FIR in

Figure 73) following the frequency translation stage. After the

carrier of interest is tuned down to dc (carrier frequency = 0 Hz),

these filters efficiently lower the sample rate, while providing

sufficient alias rejection from unwanted adjacent carriers

around the bandwidth of interest.

HB1 FIR is always enabled and cannot be bypassed. The HB2,

HB3, and HB4 FIR filters are optional and can be bypassed for

higher output sample rates.

Table 16 shows the different bandwidths selectable by including

different half-band filters. In all cases, the DDC filtering stage

on the AD6684 provides <−0.001 dB of pass-band ripple and

>100 dB of stop-band alias rejection.

Table 17 shows the amount of stop-band alias rejection for

multiple pass-band ripple/cutoff points. The decimation ratio of

the filtering stage of each DDC can be controlled individually

through Bits[1:0] of the DDC control registers (Register 0x0310

and Register 0x0330) in conjunction with the pair index register

(Register 0x0009).

Table 16. DDC Filter Characteristics

Half Band

Filter

Selection

Real Output

Complex (I/Q) Output

Alias

Protected

Bandwidth

(MHz)

Ideal SNR

Improvement1

(dB)

Pass-Band

Ripple (dB)

Alias

Rejection

(dB)

Decimation

Ratio

Output

Sample

Rate

(MSPS)

Decimation

Ratio

Output

Sample

Rate

(MSPS)

HB1

500

250 (I) +

250 (Q)

200

<−0.0001

>100

HB1 + HB2

250

125 (I) +

125 (Q)

100

HB1 + HB2 +

HB3

125

62.5 (I) +

62.5 (Q)

HB1 + HB2 +

HB3 + HB4

62.5

31.25 (I) +

31.25 (Q)

1 Ideal SNR improvement due to oversampling and filtering = 10log(bandwidth/(fS/2)).

Table 17. DDC Filter Alias Rejection

Alias Rejection

(dB)

Pass-Band Ripple/Cutoff

Point (dB)

Alias Protected Bandwidth for Real

(I) Outputs1

Alias Protected Bandwidth for Complex

(I/Q) Outputs

>100

<−0.0001

<40% × fOUT

<80% × fOUT

<−0.0002

<40.12% × fOUT

<80.12% × fOUT

<−0.0003

<40.23% × fOUT

<80.46% × fOUT

<−0.0005

<40.36% × fOUT

<80.72% × fOUT

<−0.0009

<40.53% × fOUT

<81.06% × fOUT

25.07

−0.5

45.17% × fOUT

90.34% × fOUT

19.3

−1.0

46.2% × fOUT

92.4% × fOUT

10.7

−3.0

48.29% × fOUT

96.58% × fOUT

1 fOUT = ADC input sample rate ÷ DDC decimation.

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