AD6684 datasheet(86/107 Pages) AD

86 / 107 page

AD6684

Data Sheet

Rev. 0 | Page 86 of 107

Address

Name

Bits

Bit Name

Settings

Description

Reset

Access

0x011A

Clock

detection

control

[7:5]

Reserved

Reserved.

0x0

R/W

[4:3]

Clock detection threshold

Clock detection threshold.

0x1

R/W

200 MHz.

150 MHz.

Clock detection enable

0x1

R/W

Enable.

Disable.

[1:0]

Reserved.

0x2

R/W

0x011B

Pair map

clock status

[7:1]

Reserved

Reserved.

0x0

Input clock detect

Clock detection status.

0x0

Input clock not detected.

Input clock detected/locked.

0x011C

Clock DCS

control

[7:3]

Reserved

Reserved.

0x1

R/W

Clock DCS enable

Clock DCS enable.

0x0

R/W

DCS bypassed.

DCS enabled.

Clock DCS power-up

Clock DCS power-up.

0x0

R/W

DCS powered down.

DCS powered up. The DCS must be

powered up before being enabled.

0x0120

Pair map

SYSREF

Control 1

Reserved

Reserved.

0x0

SYSREF± flag reset

Normal flag operation.

0x0

R/W

SYSREF± flags held in reset (setup/hold

error flags cleared).

Reserved

Reserved.

0x0

SYSREF± transition select

SYSREF± is valid on low to high transitions

using the selected CLK input edge. When

changing this setting, the SYSREF± mode

select must be set to disabled.

0x0

R/W

SYSREF± is valid on high to low transitions

using the selected CLK input edge. When

changing this setting, the SYSREF± mode

select must be set to disabled.

CLK± edge select

Captured on rising edge of CLK input.

0x0

R/W

Captured on falling edge of CLK input.

[2:1]

SYSREF± mode select

Disabled.

0x0

R/W

Continuous.

N shot.

Reserved

Reserved.

0x0

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