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AD6684 Datasheet(PDF) 66 Page - Analog Devices

Part # AD6684
Description  135 MHz Quad IF Receiver
PDF  107 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD6684 Datasheet(HTML) 66 Page - Analog Devices

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AD6684
Data Sheet
Rev. 0 | Page 66 of 107
YES
UPDATE
SETUP/HOLD
DETECTOR STATUS
(0x0128)
INCREMENT
SYSREF± IGNORE
COUNTER
YES
NO
SYSREF±
ENABLED?
(0x0120)
NO
CLOCK
DIVIDER
> 1?
(0x010B)
YES
NO
INPUT
CLOCK
DIVIDER
ALIGNMENT
REQUIRED?
YES
NO
NO
YES
ALIGN CLOCK
DIVIDER
PHASE TO
SYSREF
SYNCHRONIZATION
MODE?
(0x01FF)
TIMESTAMP
MODE
NORMAL
MODE
YES
SYSREF±
INSERTED
IN JESD204B
CONTROL BITS
BACK TO START
NO
DDC NCO
ALIGNMENT
ENABLED?
(0x0300)
YES
NO
NO
YES
SEND K28.5
CHARACTERS
NORMAL
JESD204B
INITIALIZATION
SYSREF±
CONTROL BITS?
(0x0559, 0x055A,
0x058F)
RESET
SYSREF± IGNORE
COUNTER
NO
START
SYSREF±
ASSERTED?
YES
NO
YES
ALIGN SIGNAL
MONITOR
COUNTERS
YES
NO
NO
YES
NO
INCREMENT
SYSREF±
COUNTER
(0x012A)
SYSREF±
TIMESTAMP
DELAY
(0x0123)
BACK TO START
SYSREF±
IGNORE
COUNTER
EXPIRED?
(0x0121)
CLOCK
DIVIDER
AUTO ADJUST
ENABLED?
(0x0108)
RAMP
TEST
MODE
ENABLED?
(0x0550)
SYSREF± RESETS
RAMP TEST
MODE
GENERATOR
JESD204B
LMFC
ALIGNMENT
REQUIRED?
ALIGN PHASE
OF ALL
INTERNAL CLOCKS
(INCLUDING LMFC)
TO SYSREF±
SEND INVALID
8-BIT/10-BIT
CHARACTERS
(ALL ZEROS)
SYNC~
ASSERTED
SIGNAL
MONITOR
ALIGNMENT
ENABLED?
(0x026F)
ALIGN DDC
NCO PHASE
ACCUMULATOR
Figure 101. Multichip Synchronization



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