AD6684 datasheet(13/107 Pages) AD

13 / 107 page

Data Sheet

AD6684

Rev. 0 | Page 13 of 107

Pin No.

Mnemonic

Type

Description

23, 24

SERDOUTAB0−,

SERDOUTAB0+

Output

Lane 0 Output Data Complement/True for Channel A and

Channel B.

25, 26

SERDOUTAB1−,

SERDOUTAB1+

Output

Lane 1 Output Data Complement/True for Channel A and

Channel B.

27, 28

SERDOUTCD1+,

SERDOUTCD1−

Output

Lane 1 Output Data True/Complement for Channel C and

Channel D.

29, 30

SERDOUTCD0+,

SERDOUTCD0−

Output

Lane 0 Output Data True/Complement for Channel C and

Channel D.

SYNCINB+CD

Input

Active Low JESD204B LVDS/CMOS Sync Input True for Channel C

and Channel D.

SYNCINB−CD

Input

Active Low JESD204B LVDS Sync Input Complement for

Channel C and Channel D.

SDIO

Input/output

SPI Serial Data Input/Output.

SCLK

Input

SPI Serial Clock.

CSB

Input

SPI Chip Select (Active Low).

SPIVDD

Supply

Digital Power Supply for SPI (1.8 V Nominal).

VCM_CD/VREF

Output/input

Common-Mode Level Bias Output for Analog Input Channel C

and Channel D/0.5 V Reference Voltage Input. This pin is

configurable through the SPI as an output or an input. Use

this pin as the common-mode level bias output if using the

internal reference. This pin requires a 0.5 V reference voltage

input if using an external voltage reference source.

47, 48

VIN−D, VIN+D

Input

ADC D Analog Input Complement/True.

52, 53

VIN+C, VIN−C

Input

ADC C Analog Input True/Complement.

60, 61

CLK+, CLK−

Input

Clock Input True/Complement.

63, 67

AGND_SR

Ground

Ground Reference for SYSREF±.

AVDD1_SR

Supply

Analog Power Supply for SYSREF± (0.975 V Nominal).

65, 66

SYSREF+, SYSREF−

Input

Active Low JESD204B LVDS System Reference (SYSREF) Input

True/Complement. DC-coupled input only.

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