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AD6684 Datasheet(PDF) 104 Page - Analog Devices

Part # AD6684
Description  135 MHz Quad IF Receiver
PDF  107 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD6684 Datasheet(HTML) 104 Page - Analog Devices

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AD6684
Data Sheet
Rev. 0 | Page 104 of 107
Address
Name
Bits
Bit Name
Settings
Description
Reset
Access
0x05C6
JESD204B
serializer
preemphasis
selection
register for
Logical
Lane 1
7
Post tab polarity
Post tab polarity.
0x0
R/W
0
Normal.
1
Inverted.
[6:4]
Sets post tab level
These bits set the post tab level.
0x0
R/W
0
0 dB.
1
3 dB.
10
6 dB.
11
9 dB.
100
12 dB.
101
Not valid.
110
Not valid.
111
Not valid.
3
Pretab polarity
This bit sets the pretab polarity.
0x0
R/W
0
Normal.
1
Inverted.
[2:0]
Sets pretab level
These bits set the pretab level.
0x0
R/W
0
0 dB.
1
3 dB.
10
6 dB.
11
9 dB.
100
12 dB.
101
Not valid.
110
Not valid.
111
Not valid.
0x0922
Large dither
control
[7:0]
Large dither control
Enables/disables the large dither control.
0x70
R/W
1110000
Enable.
1110001
Disable.
0x1222
PLL
calibration
[7:0]
PLL calibration
PLL calibration.
0x0
R/W
0x00
Normal operation.
0x04
PLL calibration
0x1228
JESD204B
start-up
circuit reset
[7:0]
JESD204B start-up circuit
reset
JESD204B start-up circuit reset.
0xF
R/W
0x0F
Normal operation.
0x4F
Start-up circuit reset.
0x1262
PLL loss of
lock control
PLL loss of lock control
PLL loss of lock control.
0x0
R/W
0x00
Normal operation.
0x08
Clear loss of lock.
0x18A6
Pair map
VREF control
[7:5]
Reserved
Reserved.
0x0
R
4
Reserved
Reserved.
0x0
R/W
[3:1]
Reserved
Reserved.
0x0
R
0
VREF control
0x0
R/W
0
Internal reference.
1
External reference.
0x1908
Channel
map analog
input
control
[7:6]
Reserved
Reserved.
0x0
R
[5:4]
Reserved
Reserved.
0x0
R/W
3
Reserved
Reserved.
0x0
R
2
Analog input dc coupling
control
Analog input dc coupling control.
0x0
R/W
0
AC coupling.
1
DC coupling.
1
Reserved
Reserved.
0x0
R
0
Reserved
Reserved.
0x0
R/W



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