AD6684 datasheet(102/107 Pages) AD

102 / 107 page

AD6684

Data Sheet

Rev. 0 | Page 102 of 107

Address

Name

Bits

Bit Name

Settings

Description

Reset

Access

0x058F

JESD204B

map JTX CS

N config-

uration

[7:6]

Number of control bits (CS)

per sample

0x0

R/W

No control bits (CS = 0).

One control bit (CS = 1), Control Bit 2 only.

Two control bits (CS = 2), Control Bit 2 and

Control Bit 1 only.

Three control bits (CS = 3), all control bits

(Bits[2:0]).

Reserved

Reserved.

0x0

[4:0]

ADC converter resolution (N)

0xF

R/W

00110

N = 7-bit resolution.

00111

N = 8-bit resolution.

01000

N = 9-bit resolution.

01001

N = 10-bit resolution.

01010

N = 11-bit resolution.

01011

N = 12-bit resolution.

01100

N = 13-bit resolution.

01101

N = 14-bit resolution.

01110

N = 15-bit resolution.

01111

N = 16-bit resolution.

0x0590

JESD204B

map JTX

SCV NP

config-

uration

[7:5]

Subclass support

0x1

R/W

000

Subclass 0.

001

Subclass 1.

[4:0]

ADC number of bits per

sample (N')

0xF

R/W

00111

N' = 8.

01111

N' = 16.

0x0591

JESD204B

map JTX JV

S config-

uration

[7:5]

Reserved

Reserved.

0x1

[4:0]

Samples per converter

frame cycle (S)

Samples per converter frame cycle

(S = Register 0x0591, Bits[4:0] + 1).

0x0

0x0592

JESD204B

map JTX HD

CF config-

uration

HD value

0x0

High density format disabled.

High density format enabled.

[6:5]

Reserved

Reserved.

0x0

[4:0]

Control words per frame

clock cycle per link (CF)

Number of control words per frame clock

cycle per link (CF = Register 0x0592, Bits[4:0]).

0x0

0x05A0

JESD204B

map JTX

Checksum 0

config-

uration

[7:0]

Checksum 0 checksum

value for SERDOUTAB0±/

SERDOUTCD0±

Serial checksum value for Lane 0, auto-

matically calculated for each lane. Sum (all

link configuration parameters for Lane 0)

mod 256.

0xC3

0x05A1

JESD204B

map JTX

Checksum 1

config-

uration

[7:0]

Checksum 1 checksum

value for SERDOUTAB1±/

SERDOUTCD1±

Serial checksum value for Lane 1, auto-

matically calculated for each lane. Sum (all

link configuration parameters for Lane 1)

mod 256.

0xC4

0x05B0

JESD204B

Map JTX

Lane power-

down

[7:3]

Reserved

Reserved.

0x1F

R/W

JESD204B Lane 1 power-

down

Physical Lane 1 force power-down.

0x0

R/W

Reserved

Reserved.

0x1

R/W

JESD204B lane 0 power-

down

Physical Lane 0 force power-down.

0x0

R/W

AD6684 Datasheet(PDF) 102 Page - Analog Devices

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