AD9559PCBZ datasheet(104/120 Pages) AD

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AD9559

Data Sheet

Rev. 0 | Page 104 of 120

Table 154. IRQ Clearing for Digital PLL1 (DPLL_1)

Address

Bits

Bit Name

Description

0x0A0C

Frequency unclamp

Clears IRQ indicating that DPLL_1 has exited a frequency clamped state

Frequency clamp

Clears IRQ indicating that DPLL_1 has entered a frequency clamped state

Phase slew unlimited

Clears IRQ indicating that DPLL_1 has exited a phase slew limited state

Phase slew limited

Clears IRQ indicating that DPLL_1 has entered a phase slew limited state

Frequency unlocked

Clears IRQ indicating that DPLL_1 has lost frequency lock

Frequency locked

Clears IRQ indicating that DPLL_1 has acquired frequency lock

Phase unlocked

Clears IRQ indicating that DPLL_1 has lost phase lock

Phase locked

Clears IRQ indicating that DPLL_1 has acquired phase lock

0x0A0D

DPLL_1 switching

Clears IRQ indicating that DPLL_1 is switching to a new reference

DPLL_1 free run

Clears IRQ indicating that DPLL_1 has entered free run mode

DPLL_1 holdover

Clears IRQ indicating that DPLL_1 has entered holdover mode

History updated

Clears IRQ indicating that DPLL_1 has updated its tuning word history

REFD activated

Clears IRQ indicating that DPLL_1 has activated REFD

REFC activated

Clears IRQ indicating that DPLL_1 has activated REFC

REFB activated

Clears IRQ indicating that DPLL_1 has activated REFB

REFA activated

Clears IRQ indicating that DPLL_1 has activated REFA

0x0A0E

[7:5]

Reserved

Sync distribution

Clears IRQ indicating a distribution sync event

APLL_1 unlocked

Clears IRQ indicating that APLL_1 has been unlocked

APLL_1 locked

Clears IRQ indicating that APLL_1 has been locked

APLL_1 cal complete

Clears IRQ indicating that APLL_1 calibration complete

APLL_1 cal started

Clears IRQ indicating that APLL_1 calibration started

PLL_0 OPERATIONAL CONTROLS (REGISTER 0x0A20 TO REGISTER 0x0A24)

Table 155. PLL_0 Sync and Calibration

Address

Bits

Bit Name

Description

0x0A20

[7:3]

Reserved

Default: 0x0

APLL_0 soft sync

Setting this bit initiates synchronization of the clock distribution output. Default: 0b.

Nonmasked outputs stall when value is 1; restart is initialized on a 1-to-0 transition.

APLL_0 calibrate

(not self-clearing)

1 = initiates VCO calibration (calibration occurs on a 0-to-1 transition).

0 (default) = does nothing.

This bit is not an autoclearing bit.

PLL_0 power-down

Places DPLL_0, APLL_0, and PLL_0 clock in deep sleep mode.

Default: the device is not powered down.

Table 156. PLL_0 Output Disable

Address

Bits

Bit Name

Description

0x0A21

[7:4]

Reserved

Default 0x0

OUT0B disable

Setting this bit puts the only OUT0B driver into power-down. Default: 0b.

Channel synchronization is maintained, but runt pulses may be generated.

OUT0A disable

Setting this bit puts the only OUT0A driver into power-down. Default: 0b.

Channel synchronization is maintained, but runt pulses may be generated.

OUT0B channel power-down

Setting this bit puts the OUT0B divider and driver into power-down. Default: 0b.

This mode saves the most power, but runt pulses may be generated during exit.

OUT0A channel power-down

Setting this bit puts the OUT0A divider and driver into power-down. Default: 0b.

This mode saves the most power, but runt pulses may be generated during exit.

AD9559PCBZ Datasheet(PDF) 104 Page - Analog Devices

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