AD9559PCBZ datasheet(108/120 Pages) AD

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AD9559

Data Sheet

Rev. 0 | Page 108 of 120

Table 167. Status of Reference Inputs

Address

Bits

Bit Name

Description

0x0D02

[7:6]

Reserved

Default: 00b.

DPLL_1 REFA active

This bit is 1 if DPLL_1 is either locked to or attempting to lock to REFA.

DPLL_0 REFA active

This bit is 1 if DPLL_0 is either locked to or attempting to lock to REFA.

REFA valid

This bit is 1 if the REFA frequency is within the programmed limits.

REFA fault

This bit is 1 if the REFA frequency is outside of the programmed limits.

REFA fast

This bit is 1 if the REFA frequency is higher than allowed by its profile settings.

REFA slow

This bit is 1 if the REFA frequency is lower than allowed by its profile settings.

0x0D03

[7:6]

Reserved

Default: 00b.

DPLL_1 REFB active

This bit is 1 if DPLL_1 is either locked to or attempting to lock to REFB.

DPLL_0 REFB active

This bit is 1 if DPLL_0 is either locked to or attempting to lock to REFB.

REFB valid

This bit is 1 if the REFB frequency is within the programmed limits.

REFB fault

This bit is 1 if the REFB frequency is outside of the programmed limits.

REFB fast

This bit is 1 if the REFB frequency is higher than allowed by its profile settings.

REFB slow

This bit is 1 if the REFB frequency is lower than allowed by its profile settings.

0x0D04

[7:6]

Reserved

Default: 00b.

DPLL_1 REFC active

This bit is 1 if DPLL_1 is either locked to or attempting to lock to REFC.

DPLL_0 REFC active

This bit is 1 if DPLL_0 is either locked to or attempting to lock to REFC.

REFC valid

This bit is 1 if the REFC frequency is within the programmed limits.

REFC fault

This bit is 1 if the REFC frequency is outside of the programmed limits.

REFC fast

This bit is 1 if the REFC frequency is higher than allowed by its profile settings.

REFC slow

This bit is 1 if the REFC frequency is lower than allowed by its profile settings.

0x0D05

[7:6]

Reserved

Default: 00b.

DPLL_1 REFD active

This bit is 1 if DPLL_1 is either locked to or attempting to lock to REFD.

DPLL_0 REFD active

This bit is 1 if DPLL_0 is either locked to or attempting to lock to REFD.

REFD valid

This bit is 1 if the REFD frequency is within the programmed limits.

REFD fault

This bit is 1 if the REFD frequency is outside of the programmed limits.

REFD fast

This bit is 1 if the REFD frequency is higher than allowed by its profile settings.

REFD slow

This bit is 1 if the REFD frequency is lower than allowed by its profile settings.

IRQ MONITOR (REGISTER 0x0D08 TO REGISTER 0x0D10)

If not masked via the IRQ mask registers (Register 0x010A to Register 0x0112), the appropriate IRQ monitor bit is set to Logic 1 when the

indicated event occurs. These bits can be cleared only by a device reset, or by setting the clear all IRQs bit in Register 0x0A05, or by

setting the IRQ clearing registers (Register 0x0A05 to Register 0x0A0E).

Table 168. IRQ for Common Functions

Address

Bits

Bit Name

Description

0x0D08

Reserved

SYSCLK unlocked

IRQ indicating a SYSCLK PLL state transition from locked to unlocked

SYSCLK stable

IRQ indicating that SYSCLK stability time has expired and that the SYSCLK PLL is

considered to be stable

SYSCLK locked

IRQ indicating a SYSCLK PLL state transition from unlocked to locked

Watchdog timer

IRQ indicating expiration of the watchdog timer

Reserved

EEPROM fault

IRQ indicating a fault during an EEPROM load or save operation

EEPROM complete

IRQ indicating successful completion of an EEPROM load or save operation

AD9559PCBZ Datasheet(PDF) 108 Page - Analog Devices

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