AD9559PCBZ datasheet(112/120 Pages) AD

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AD9559

Data Sheet

Rev. 0 | Page 112 of 120

PLL_1 READ-ONLY STATUS (REGISTER 0x0D40 TO REGISTER 0x0D4A)

All bits in Register 0x0D40 to Register 0x0D4A are read only. To report the latest status, these bits require an IO_UPDATE (Register 0x0005 =

0x01) immediately before being read.

Table 175. PLL_1 Lock Status

Address

Bits

Bit Name

Description

0x0D40

[7:5]

Reserved

Default: 000b

APLL_1

cal in progress

The control logic holds this bit set while the calibration of the APLL_1 VCO is in progress.

APLL_1 locked

Indicates the status of APLL_1.

0 = unlocked.

1 = locked.

DPLL_1 frequency lock

Indicates the frequency lock status of DPLL_1.

0 = unlocked.

1 = locked.

DPLL_1 phase lock

Indicates the phase lock status of DPLL_1.

0 = unlocked.

1 = locked.

PLL_1 all locked

Indicates the status of the system clock, APLL_1, and DPLL_1.

0 = system clock PLL or APLL_1 or DPLL_1 is unlocked.

1 = all three PLLs (system clock PLL, APLL_1, and DPLL_1) are locked.

Table 176. DPLL_1 Loop State

Address

Bits

Bit Name

Description

0x0D41

[7:5]

Reserved

Default: 000b.

[4:3]

DPLL_1 active ref

Indicates the reference input that DPLL_0 is using.

00 = DPLL_1 has selected REFA.

01 = DPLL_1 has selected REFB.

10 = DPLL_1 has selected REFC.

11 = DPLL_1 has selected REFD.

DPLL_1 switching

Indicates that DPLL_1 is switching input references.

0 = DPLL is not switching.

1 = DPLL is switching input references.

DPLL_1 holdover

Indicates that DPLL_1 is in holdover mode.

0 = not in holdover mode.

1 = in holdover mode.

DPLL_1 free run

Indicates that DPLL_1 is in free run mode.

0 = not in free run mode.

1 = in free run mode.

0x0D42

[7:3]

Reserved

Default: 00000b.

DPLL_1 phase slew limited

The control logic sets this bit when DPLL_1 is phase-slew limited.

DPLL_1 frequency clamped

The control logic sets this bit when DPLL_1 is frequency clamped.

DPLL_1 history updated

The control logic sets this bit when the tuning word history of DPLL_1 is available.

(See Register 0x0D43 to Register 0x0D46 for the tuning word.)

Table 177. DPLL_1 Holdover History

Address

Bits

Bit Name

Description

0x0D43

[7:0]

DPLL_0 tuning word

readback

DPLL_1 tuning word readback bits, Bits[7:0]. This group of registers contains the averaged

digital PLL tuning word used when the DPLL enters holdover. Setting the history

accumulation timer to its minimal value allows the user to use these registers for

a readback of the most recent DPLL tuning word without averaging.

0x0D44

[7:0]

DPLL_1 tuning word readback, Bits[15:8].

0x0D45

[7:0]

DPLL_1 tuning word readback, Bits[23:9].

0x0D46

[7:6]

Reserved.

[5:0]

DPLL_1 tuning word readback, Bits[29:24].

AD9559PCBZ Datasheet(PDF) 112 Page - Analog Devices

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