AD9559PCBZ datasheet(115/120 Pages) AD

115 / 120 page

Data Sheet

AD9559

Rev. 0 | Page 115 of 120

Table 183. EEPROM Storage Sequence for DPLL_0 General Settings

Address

Bits

Bit Name

Description

0x0E27

[7:0]

DPLL_0

general settings

The default value of this register is 0x15, which the controller interprets as a data instruction. Its

decimal value is 21, which tells the controller to transfer 22 bytes of data (21 + 1), beginning at the

address specified by the next two bytes. The controller stores 0x15 in the EEPROM and increments

the EEPROM address pointer.

0x0E28

[7:0]

The default value of these two registers is 0x0400. Because the previous register contains a data

instruction, these two registers define a starting address (in this case, 0x0400). The controller stores

0x0400 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 22 bytes from the

pointer by 23 (22 data bytes and one checksum byte). The 22 bytes transferred correspond to the

DPLL_0 general settings (for example, free running tuning word) in the register map.

0x0E29

[7:0]

Table 184. EEPROM Storage Sequence for APLL_0 Configuration and Output Drivers

Address

Bits

Bit Name

Description

0x0E2A

[7:0]

APLL_0

config and

output drivers

The default value of this register is 0x0E, which the controller interprets as a data instruction. Its

decimal value is 14, which tells the controller to transfer 15 bytes of data (14 + 1) beginning at the

address specified by the next two bytes. The controller stores 0x0E in the EEPROM and increments

the EEPROM address pointer.

0x0E2B

[7:0]

The default value of these two registers is 0x0420. Because the previous register contains a data

instruction, these two registers define a starting address (in this case, 0x0420). The controller stores

0x0420 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 15 bytes from the

pointer by 16 (15 data bytes and one checksum byte). The 15 bytes transferred correspond to the

APLL_0 settings as well as the PLL_0 output driver settings in the register map.

0x0E2C

[7:0]

Table 185. EEPROM Storage Sequence for PLL_0 Dividers and BW Settings

Address

Bits

Bit Name

Description

0x0E2D

[7:0]

DPLL_0

dividers and BW

The default value of this register is 0x33, which the controller interprets as a data instruction. Its

decimal value is 51, which tells the controller to transfer 52 bytes of data (51 + 1), beginning at the

address specified by the next two bytes. The controller stores 0x33 in the EEPROM and increments

the EEPROM address pointer.

0x0E2E

[7:0]

The default value of these two registers is 0x0440. Because the previous register contains a data

instruction, these two registers define a starting address (in this case, 0x0440). The controller stores

0x0440 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 52 bytes from the

pointer by 53 (52 data bytes and one checksum byte). The 52 bytes transferred correspond to the

DPLL_0 feedback dividers and loop BW settings in the register map.

0x0E2F

[7:0]

Table 186. EEPROM Storage Sequence for DPLL_1 General Settings

Address

Bits

Bit Name

Description

0x0E30

[7:0]

DPLL_1

general settings

The default value of this register is 0x15, which the controller interprets as a data instruction. Its

decimal value is 21, which tells the controller to transfer 22 bytes of data (21 + 1), beginning at the

address specified by the next two bytes. The controller stores 0x15 in the EEPROM and increments

the EEPROM address pointer.

0x0E31

[7:0]

The default value of these two registers is 0x0500. Because the previous register contains a data

instruction, these two registers define a starting address (in this case, 0x0500). The controller stores

0x0500 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 22 bytes from the

pointer by 23 (22 data bytes and one checksum byte). The 22 bytes transferred correspond to the

DPLL_1 general settings (for example, free running tuning word) in the register map.

0x0E32

[7:0]

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