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AD9559PCBZ Datasheet(PDF) 119 Page - Analog Devices |
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AD9559PCBZ Datasheet(HTML) 119 Page - Analog Devices |
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119 / 120 page  Data Sheet AD9559 Rev. 0 | Page 119 of 120 Table 197. Multifunction Pin Input Functions (D7 = 0) Bits[D7:D0] Value Output Function Destination Proxy 0x00 Reserved—high-Z input None 0x01 IO_UPDATE Register 0x0005, Bit 0 0x02 Full power-down Register 0x0A00, Bit 0 0x03 Clear watchdog timer Register 0x0A05, Bit 7 0x04 Sync all channel dividers Register 0x0A00, Bit 2 0x10 Clear all IRQs Register 0x0A05, Bit 0 0x11 Clear common IRQs Register 0x0A05, Bit 1 0x12 Clear DPLL_0 IRQs Register 0x0A05, Bit 2 0x13 Clear DPLL_1 IRQs Register 0x0A05, Bit 3 0x20/0x21/0x22/0x23 Force fault REFA/REFB/REFC/REFD Register 0x0A03, Bits[3:0] 0x28/0x29/0x2A/0x2B Force validation timeout REFA/REFB/REFC/REFD Register 0x0A02, Bits[3:0] 0x40 PLL_0 power-down Register 0x0A20, Bit 0 0x41 DPLL_0 user free run Register 0x0A22, Bit 0 0x42 DPLL_0 user holdover Register 0x0A22, Bit 1 0x43 DPLL_0 tuning word history reset Register 0x0A23, Bit 1 0x44 DPLL_0 increment incremental phase offset Register 0x0A24, Bit 0 0x45 DPLL_0 decrement incremental phase offset Register 0x0A24, Bit 1 0x46 DPLL_0 reset incremental phase offset Register 0x0A24, Bit 2 0x48 APLL_0 sync clock distribution outputs Register 0x0A20, Bit 2 0x49 PLL_0 disable all output drivers Register 0x0A21, Bits[3:2] 0x4A PLL_0 disable OUT0A Register 0x0A21, Bit 2 0x4B PLL_0 disable OUT0B Register 0x0A21, Bit 3 0x4C PLL_0 manual reference input selection, Bit 0 Register 0x0A22, Bit 5 0x4D PLL_0 manual reference input selection, Bit 1 Register 0x0A22, Bit 6 0x50 PLL_1 power-down Register 0x0A40, Bit 0 0x51 DPLL_1 user free run Register 0x0A42, Bit 0 0x52 DPLL_1 user holdover Register 0x0A42, Bit 1 0x53 DPLL_1 tuning word history reset Register 0x0A43, Bit 1 0x54 DPLL_1 increment incremental phase offset Register 0x0A44, Bit 0 0x55 DPLL_1 decrement incremental phase offset Register 0x0A44, Bit 1 0x56 DPLL_1 reset incremental phase offset Register 0x0A44, Bit 2 0x58 APLL_1 sync clock distribution outputs Register 0x0A40, Bit 2 0x59 PLL_1 disable all output drivers Register 0x0A41, Bits[3:2] 0x5A PLL_1 disable OUT1A Register 0x0A41, Bit 2 0x5B PLL_1 disable OUT1B Register 0x0A41, Bit 3 0x5C PLL_1 manual reference input selection, Bit 0 Register 0x0A42, Bit 5 0x5D PLL_1 manual reference input selection, Bit 1 Register 0x0A42, Bit 6 0x5E to 0x7F Reserved |
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