AD9559PCBZ datasheet(116/120 Pages) AD

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AD9559

Data Sheet

Rev. 0 | Page 116 of 120

Table 187. EEPROM Storage Sequence for APLL_1 Configuration and Output Drivers

Address

Bits

Bit Name

Description

0x0E33

[7:0]

APLL_1 config

and output

drivers

The default value of this register is 0x0E, which the controller interprets as a data instruction. Its

decimal value is 14, which tells the controller to transfer 15 bytes of data (14 + 1) beginning at the

address specified by the next two bytes. The controller stores 0x0E in the EEPROM and increments

the EEPROM address pointer.

0x0E34

[7:0]

The default value of these two registers is 0x0520. Because the previous register contains a data

instruction, these two registers define a starting address (in this case, 0x0520). The controller stores

0x0520 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 15 bytes from the

pointer by 16 (15 data bytes and one checksum byte). The 15 bytes transferred correspond to the

APLL_1 settings as well as the PLL_1 output driver settings in the register map.

0x0E35

[7:0]

Table 188. EEPROM Storage Sequence for PLL_1 Dividers and BW Settings

Address

Bits

Bit Name

Description

0x0E36

[7:0]

DPLL_1 dividers

and BW

The default value of this register is 0x33, which the controller interprets as a data instruction. Its

decimal value is 52, which tells the controller to transfer 53 bytes of data (52 + 1), beginning at the

address specified by the next two bytes. The controller stores 0x33 in the EEPROM and increments

the EEPROM address pointer.

0x0E37

[7:0]

The default value of these two registers is 0x0540. Because the previous register contains a data

instruction, these two registers define a starting address (in this case, 0x0540). The controller stores

0x0540 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 53 bytes from the

pointer by 54 (53 data bytes and one checksum byte). The 53 bytes transferred correspond to the

DPLL_1 feedback dividers and loop BW settings in the register map.

0x0E38

[7:0]

Table 189. EEPROM Storage Sequence for Loop Filter Settings

Address

Bits

Bit Name

Description

0x0E39

[7:0]

Loop filter

The default value of this register is 0x17, which the controller interprets as a data instruction. Its

decimal value is 23, which tells the controller to transfer 24 bytes of data (23 + 1), beginning at the

address specified by the next two bytes. The controller stores 0x17 in the EEPROM and increments

the EEPROM address pointer.

0x0E3A

[7:0]

The default value of these two registers is 0x0800. Because the previous register contains a data

instruction, these two registers define a starting address (in this case, 0x0800). The controller stores

0x0800 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 24 bytes from the

pointer by 25 (24 data bytes and one checksum byte). The 24 bytes transferred are the loop filter

settings in the register map.

0x0E3B

[7:0]

Table 190. EEPROM Storage Sequence for Common Operational Control Settings

Address

Bits

Bit Name

Description

0x0E3C

[7:0]

Common

operational

controls

The default value of this register is 0x0E, which the controller interprets as a data instruction. Its

decimal value is 14, which tells the controller to transfer 15 bytes of data (14 + 1), beginning at the

address specified by the next two bytes. The controller stores 0x0E in the EEPROM and increments

the EEPROM address pointer.

0x0E3D

[7:0]

The default value of these two registers is 0x0A00. Because the previous register contains a data

instruction, these two registers define a starting address (in this case, 0x0A00). The controller stores

0x0A00 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 15 bytes from the

pointer by 16 (15 data bytes and one checksum byte). The 15 bytes transferred correspond to the

common operational controls in the register map.

0x0E3E

[7:0]

AD9559PCBZ Datasheet(PDF) 116 Page - Analog Devices

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