AD9559PCBZ datasheet(117/120 Pages) AD

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Data Sheet

AD9559

Rev. 0 | Page 117 of 120

Table 191. EEPROM Storage Sequence for PLL_0 Operational Control Settings

Address

Bits

Bit Name

Description

0x0E3F

[7:0]

PLL_0

operational

controls

The default value of this register is 0x04, which the controller interprets as a data instruction. Its

decimal value is 4, which tells the controller to transfer five bytes of data (4 + 1), beginning at the

address specified by the next two bytes. The controller stores 0x04 in the EEPROM and increments

the EEPROM address pointer.

0x0E40

[7:0]

The default value of these two registers is 0x0A20. Because the previous register contains a data

instruction, these two registers define a starting address (in this case, 0x0A20). The controller stores

0x0A20 in the EEPROM and increments the EEPROM pointer by 2. It then transfers five bytes from

the register map (beginning at Address 0x0A20) to the EEPROM and increments the EEPROM

address pointer by six (five data bytes and one checksum byte). The five bytes transferred

correspond to the PLL_0 operational controls in the register map.

0x0E41

[7:0]

Table 192. EEPROM Storage Sequence for PLL_1 Operational Control Settings

Address

Bits

Bit Name

Description

0x0E42

[7:0]

PLL_1

operational

controls

The default value of this register is 0x04, which the controller interprets as a data instruction. Its

decimal value is 4, which tells the controller to transfer five bytes of data (4 + 1), beginning at the

address specified by the next two bytes. The controller stores 0x04 in the EEPROM and increments

the EEPROM address pointer.

0x0E43

[7:0]

The default value of these two registers is 0x0A40. Because the previous register contains a data

instruction, these two registers define a starting address (in this case, 0x0A40). The controller stores

0x0A40 in the EEPROM and increments the EEPROM pointer by 2. It then transfers five bytes from

the register map (beginning at Address 0x0A40) to the EEPROM and increments the EEPROM

address pointer by six (five data bytes and one checksum byte). The five bytes transferred

correspond to the PLL_1 operational controls in the register map.

0x0E44

[7:0]

Table 193. EEPROM Storage Sequence for APLL Calibration

Address

Bits

Bit Name

Description

0x0E45

[7:0]

IO_UPDATE

The default value of this register is 0x80, which the controller interprets as an IO_UPDATE instruction.

The controller stores 0x80 in the EEPROM and increments the EEPROM address pointer.

0x0E46

[7:0]

Calibrate APLLs

The default value of this register is 0x90, which the controller interprets as a calibrate instruction for

both APLLs. The controller stores 0x90 in the EEPROM and increments the EEPROM address pointer.

0x0E47

[7:0]

Sync outputs

The default value of this register is 0xA0, which the controller interprets as a distribution sync

instruction for all of the output dividers. The controller stores 0xA0 in the EEPROM and increments

the EEPROM address pointer.

Table 194. EEPROM Storage Sequence for End of Data

Address

Bits

Bit Name

Description

0x0E48

[7:0]

End of data

The default value of this register is 0xFF, which the controller interprets as an end instruction. The

controller stores this instruction in the EEPROM, resets the EEPROM address pointer, and enters an

idle state.

Note that if the user replaces this command with a pause rather than an end instruction, the

controller actions are the same except that the controller increments the EEPROM address pointer

rather than resetting it. This allows the user to store multiple EEPROM profiles in the EEPROM.

Table 195. Unused

Address

Bits

Bit Name

Description

0x0E49 to

0x0E4F

[7:0]

Unused

This area is unused in the default configuration and is available for additional EEPROM storage

sequence commands. Note that the EEPROM storage sequence should always end with either an

end of data or pause command.

AD9559PCBZ Datasheet(PDF) 117 Page - Analog Devices

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